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Question & Answer

EPR wants to be your partner in design, production and knowledge. We think that knowledge is most valuable when shared. That’s why you can ask us a technical question on every Monday through social media or by email. We aim to provide you with an answer to that question that same week.

Out of all those questions asked, we will highlight one question on our social media every Monday. The next day one of our professionals will answer the highlighted question. Click on the buttons below to find the question of the week or to check out the archive with an overview of all questions and answers discussed before.

Do you have a pressing question waiting for an answer? Please feel free to ask us! You can contact us through our social media or by sending your question to contact@eprpartner.com.

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Question of the week

Question

Why should we consider using GaN technology instead of silicon MOSFETs in power conversion applications?

Answer

GaN offers several key benefits and advantages when it comes to power density:

  • Lower RDS(on): GaN has half the RDS(on) per area compared to MOSFETs. This translates to 50% lower conduction losses. Therefore, you can use smaller heat sinks and simpler thermal management.
  • Lower gate and output charge: GaN technology offers a lower gate charge enabling designs with much faster turn-on times and slew rates, while reducing losses. A lower output charge results in two advantages to each design. First, the switching losses drop by as much as 75%, which in combination with lower conduction losses, has a major and positive impact on power density. Second, the design can run at up to 10X higher switching frequencies (depending on the application). This significantly reduces the size of magnetics as well as the size and footprint of designs, while improving overall efficiency by as much as 15%.
  • Zero reverse recovery: Silicon MOSFETs have a typ. reverse-recovery charge in the 40- to 70-nC range (depending on their size and characteristics). When a MOSFET turns off, the reverse-recovery charges (Qrr) in the internal diode will produce losses that add to the total system switching losses. These losses rise proportionally with the switching frequency. GaN has zero reverse recovery and no Qrr losses, making GaN FETs ideal for applications which use a high switching frequency.
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Archive

Here you will find an overview of all questions and answers discussed before.

Question

What issues do you have to address when using an Li-ion battery?

Answer

Nowadays Li-Ion batteries are very popular as power source or even as back-up for electronics. Ni-MH and NiCad batteries are old.

The advantage of Li-Ion batteries is that the self-discharge is very low and the energy density is high. The disadvantage is that additional protection is needed to address hazardous situations. The battery needs over charge protection as well as under discharge protection. When more Li-Ion cells are put in a chain charging and discharging is becoming even more complex because of unbalance during longer operation time. A BMC (Battery management Controller) can be used to address these issues. The nominal voltage of a Li-ion cell is about 3,7 Volt. Completely charged a cell will be 4.2 Volt. An Over voltage Protection Circuit (OVP) will protect this. Also a Li-Ion cell may not be discharge completely. An Under voltage Protection Circuit (UVP) will protect this. Furthermore the Li-ion battery must be protecting from over current charging and discharging. Adding a temperature sensor will help as an indication for over current. All this means a lot of design choices and effort must be made. Lucky for us that there are a lot of manufacturers who do have special IC’s to address these issues!

Question

What is a proper way to route high-voltage tracks near the components?

Answer

Make use of proper design rules to be sure that distances are maintained.

If the design has voltages above 750V, the type of solder mask should be adapted too.

Question

Via in between differential traces – how bad is it?

Answer

In a high-speed printed circuit board (PCB), a via is notorious for degrading signal-integrity performance. However, using via structures is unavoidable. In a typical board, components are placed on the outer layers, while differential pairs are routed in inner layers where they lower electromagnetic radiation and pair-to-pair crosstalk. Vias must be used to connect components on the board’s surface to the inner layers. Vias generally look capacitive. minimizing the annular rings and increasing the antipad diameter will help make the via look transparent. a good rule of thumb is to avoid all asymmetries in a differential pair. Whatever you do to one trace, do the same to the other.

Question

Are you using tantalum capacitors on your design?

Answer

In the past tantalum capacitors where very popular in SMPS (Switch mode power supplies) designs because of Low ESR value combined with high capacity at small size. The downside is that they are expensive and are less reliable. In the past we’ve seen a lot of shortened and exploded tantalum caps! Probably due to surge currents.

Today there are a few alternatives like MLCC and the new Niobium Oxide (NbO)capacitors. Niobium Oxide exactly looks like the old tantalum, however they are will not burn at overloads and are thus more safer. The price is roughly the same. Multi-Layer Ceramic Capacitors (MLCCs) have no temperature derating, are non-polarized, do have a wider bandwidth and a lower ESR at high frequencies. At low frequencies you could better choose for NbO or aluminum electrolytic capacitors.

Question

How do you plan routing and what are the parameters you consider while routing?

Answer

Routing is the next step after placement of most of the components. During placement consider all the main signals. These signals can be restricted in width and clearance, driven by their maximum current or signal impedance. In the routing phase always keep your applications signal in mind. Including ground planes, supplies and traces with less importance.

Question

How do you verify schematic symbols or footprints?

Answer

Verifying schematic symbols can be done by using the datasheet of the component. But keep in mind that schematic symbols can be drawn on several ways. You can choose between European or US standard or use a mix. In principle it doesn’t matter as long as the schematic symbol is build-up in a logical way and the function is easy to understand. You may choose to split the power part and put them together with all the other power parts at the bottom of the schematic page. In order to perform electrical rule check (ERC) it is a good practise to define all the component signals like Input, output, passive, etc. It is wise to put no-connect signals on not used pins. This will not generate errors when inputs are not connected. Of course you have to check the datasheet if inputs might become floated.

To verify footprints is a more important story. Your product might become not or less producible when an error has been made. The IPC-7351 describes the requirement for SMD land patterns and IPC-7251 for through hole land patterns. To create your PCB shape you may use a IPC footprint wizard like Library Expert or if available use a build-in tool from your (EDA) lay-out program. Most likely you’ll also find the footprint in the datasheet of a specific component. We prefer to use the datasheet footprint if available.

You always want to double-check if your shape is OK. The best principle is a four-eyes check. Even when you download components from the internet. For a lot of components like connectors there are 3D-shapes available on the internet. A good verification point is when placing this 3D-shape over your footprint. At that moment you have a verification check as well.

On the market there are also DfM (Design for Manufacturing) tools like Valor, GC-, Vayo, that will check your fabrication output on footprints.

Question

What are the four main categories of signal integrity problems?

Answer

The first category is best described as: signal reflections. Signals are reflected and distorted whenever the instantaneous impedance the signal ‘sees’ changes, thus the solution to this issue is to provide a signal with a constant instantaneous impedance. In PCB design this can be achieved by controlling the impedance of the interconnects. The second category is what is referred to as cross talk or signal coupling. Signal coupling arises from the magnetic and electric coupling of adjacent signal paths, such as two traces and their respective return paths on a PCB. By minimizing the mutual capacitance and inductance between the signal paths, one can minimize the amount of coupled signal. Or more practically, space the signal paths apart sufficiently to minimize magnetic coupling and minimize coupled surface to minimize electric coupling. The third main source of signal integrity problems is electromagnetic interference or more commonly known as EMI. One can simplify EMI by looking at electronics as an antenna, in the perspective of both being a transmitter as well as a receiver. By minimizing signal loop surfaces one can minimize the amount of electromagnetic radiation the signal loop emits or can receive. More practically, in PCB design this can be done by placing decoupling capacitors as close to ICs as possible and minimizing the thickness of the dielectric to their ground plane. The last category refers to something which is commonly known as rail collapse. This issue occurs in the power distribution networks (PDN) of an electrical circuit. Interconnects are never as perfect as described in most circuit diagrams, but instead have an impedance. The current flowing through the PDN to feed all the elements in the network will cause a voltage drop across the power and ground rails, meaning a deviation in the actual voltage values of the rail. By lowering the impedance of the PDN one can minimize the so called rail collapse. One way of achieving this would be to keep supply and ground traces in a PCB as wide as possible.

Question

How do you incorporate Design for Excellence (DfX) in your engineering flow?

Answer

EPR Partner has many years of experience in engineering and assembly of advanced printed circuit boards for the semiconductor, medical and many more markets. One of our success factors is the implementation of Design for eXcellence (DfX) in our partner’s product lifecycle.

But how do we incorporate this in our engineering flow? The key to success is getting involved in an early stage of the development phase. Our NPI Engineers can advise on product requirements for example to improve yield by implementing Design for Manufacturing (DfM), Assembly (DfA) and Test (DfT). Often design for Logistics (DfL) is implemented during the design stage and led by product requirements such as physical restrictions. When all requirements are clear our engineers can help our partner with co-engineering to decrease time to market and get the design first time right! Design for Cost (DfC) and reliability (DfR) are implemented in several stages of the design and production process, ranging from component and material determination up to supplier selection. The design and implemented DfX are verified by our suppliers, manufacturers and customers, as well as through the use of tooling.

Question

What is more critical on a logic input: a pull-up or a pull-down resistor?

Answer

A pull-up resistor connects unused input pins (Logic gates) to the dc supply voltage (Vcc) to keep the given input HIGH. A pull-down resistor connects unused input pins to ground (0V) to keep the given input LOW. The resistance value for a pull-up resistor is not usually that critical but must maintain the input pin voltage above VIH. The use of 10kΩ pull-up resistors are common but values can range from 1k to 100k ohms.

Pull-down resistors are a little more critical because of the low input voltage level, VIL(max)and the higher IIL current. The use of 100Ω pull-down resistors are the most common but they can range in resistive value from 50 up to 1k ohms.

The correct answer is: a pull-down resistor is more critical.